Keytek MK.4 Turnkey ESD and Latch-Up Test System

High pin count devices, including computers, servers, smart phones and digital TVs are notoriously challenging to test. The Thermo Scientific™ MK.4 ESD and Latch-Up Test System provides rapid, repeatable testing of complex, high pin count (up to 2,304 pins) devices from design through post-production qualification. The exceptional high speed performance of the MK.4 system is the ideal solution for IC structure designers, R&D engineers, and QA program managers in manufacturing and test facilities in the aerospace/defense, consumer electronics and semiconductor industries.

ESD and Latch-Up testing of electronic and electrical goods can be very expensive aspects of the design and manufacturing process. This is especially true as market demands for products that are smaller, faster and smarter become the standard rather than the exception. The MK.4 ESD and Latch-Up Test System leverages our technology and know-how gained over three decades of test system experience, as well as our in-depth participation and contributions to global regulatory bodies governing these changes, enabling our products to meet both global and industry-driven quality standards.
 

Rapid-relay-based operations:
Offers exceptional speed at least  10 times faster than mechanically driven ESD testers. 

Switching matrix:
Provides consistent ESD paths and allows any pin to be grounded, floated, vectored or connected to any of the installed V/I supplies. 

Advanced algorithms: 
Ensure accurate switching of HV, in support of pulse source technology, per recent JEDEC/ESDA trailing pulse standards.

Human Body Model:
Per ESDA/JEDEC, JS-001-2012, MIL-STD 883E, and  AEC Q100-002 25 V to 8 kV in steps of 1 V. Test to multiple industry standards in one integrated system; no changing or alignment of pulse sources.

Machine Model:
Per ESDA STM5.2, JEDEC/JESD22-A115, and AEC Q100-003, 25 V to 1.5 kV in steps of 1 V. Integrated pulse sources allow fast multi-site test execution.

Latch-up testing:
Per JEDEC/JESD 78 test pin and AEC Q100-004. Includes preconditioning, state read-back and full control of each. Latch-Up testing Vector input/export capability from standard tester platforms and parametric measurements.

Event trigger output:
Manages setup analysis with customized scope trigger capabilities. 

Up to eight separate V/I supplies (1 stimulus and 7 bias supplies):
High accuracy DUT power, curve tracing, and Latch-up stimulus available; design also provides high current capability through the V/I matrix.

Multiple self-test diagnostic routines:
Ensures system integrity throughout the entire relay matrix, right up to the test socket.

Test reports: 
Pre-stress, pre-fail (ESD) and post-fail data, as well as full curve trace and specific data point measurements. Data can be exported for statistical evaluation and presentation.

Individual pin parametrics:
Allows the user to define V/I levels, compliance ranges, and curve trace parameters for each pin individually.

Other features:

• Solid state matrix topology provides rapid, easy-to-use testing operations 
• Six independent vector voltage levels support testing complex I/O and Multi-Core products with ease
• Provides Latch-Up stimulus and device biasing 
• Offers advanced device preconditioning with six separate vector drive levels 
• Enables ESD testing of up to 12 devices at once, along with parallel curve tracing of 8/4 devices.
• Manages ancillary test equipment as required for automated testing 
• Provides flexible programming, easy-to-use automated test setups, TCP/IP communication
• Comprehensive engineering vector debug provides flexibility

- See more at: http://www.thermoscientific.com/en/product/mk-4-esd-latch-up-test-system.html#sthash.YR0SKLy5.dpuf

Meets Human Body Model (HBM) Compliance Standards:

• AEC-Q100-002-Rev.D Jul.2003
• ESDA ANSI/EOS/ESD-STM5.1-2001
• IEC 61340-3-1Ed.1.0 2002
• IEC 60749-26 Ed.1.0 2003
• JEDEC JESD22-A114E Jan 2007
• JEITA EIAJ ED-4701/300 Aug.2001 Test Method304
• MIL-STD-883G Method 3015.7 Mar.1989

Meets Machine Model (MM) Compliance Standards:

• AEC-Q100-003-REV-E  Jul.2003
• ESDA ANSI/ESD STM5.2-1999
• IEC 61340-3-2 Ed.1.0-2002
• IEC 60749-27 Ed.1.0 2003
• JEDEC JESD22-A115A Oct.1997
• JEITA EIAJ ED-4701/300 Aug.2001

NoiseKen ESS-6002 Features:

• 10V minimum output (1V step)
• A simple probe stand and test fixture plus a pair of miniature test leads meeting many different kinds of device packages <Free Board Type>
• Narrow pitch DUT can be tested in semi-automatic manner <Semi-automatic Precision Type>
• Each probe has a coaxial interface with an external measuring instrument.
• External trigger input and output terminals are provided.